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History

0.8 (2007-03-03)

PC Client

  • new plugin: I2C protocol analyzer (by Frank Kunz)
  • bug fix: GUI is properly created, eliminating occasional glitches

0.7 (2006-12-31)

FPGA

  • complex serial and parallel trigger with four stages
  • DDR inputs with only one clock (as suggested by Andreas Pi)
  • reduced delay for sampling on external clock falling edge (no inverter in clock path)
  • constraints to meet timing requirements on XC3S1000-4 in ISE 8.2
  • various code & architecture improvements (core code separation)

PC Client

  • support for new complex trigger
  • new plugin: SPI protocol analyzer (by Frank Kunz)
  • centralized loading and storing of settings for device, diagram and tools in project files
  • channel labels (by Frank Kunz)
  • command line arguments to load data and project files on start
  • bug fix: time line works properly when trigger is enabled

0.6 (2006-08-19)

FPGA

  • sampling using external clock (A2, 37) rising & falling edge (state analysis)
  • ID command for device identification
  • configurable serial port transfer rate
  • all 32 inputs bundled on a single connector (B1, 4-35)
  • output sampling signal with 50% duty cycle (B1, 40) for external modules

PC Client

  • device ID read-out on capture start to test connection and device
  • support for new hardware features
  • user configurable drawing modes: logic level, hex value and scope
  • plugin mechanism for post-processing functions
  • new plugin: convert timing analysis to state analysis
  • bug fix: zoom in and zoom out in diagram menu work again
  • bug fix: toolbar icons show up in binary only installations
  • bug fix: before/after ratio will only be used when trigger is enabled
  • bug fix: correct status bar and scale display when no timing information is available

Tester

  • tester code modified for 3.3V ATmega8L

0.5 (2006-06-18)

FPGA

  • controller split into sampler and memory to give trigger access to real samples
  • receiver can handle short commands without data
  • new command structure
  • reset functions regardless of receiver state
  • transmitter is now byte oriented with xon/xoff flow control support
  • able to exclude specific channel groups from transfer

PC Client

  • modified for new command structure
  • faster diagram drawing
  • hex value display for channel groups
  • handles unresponsive device & cancels better
  • more precise trigger position calculation
  • status bar providing information on the diagram
  • various bug fixes

0.4 (2006-05-23)

FPGA

  • uses more precise 100MHz DDR mechanism for filter and demux instead of 200MHz clock (requires only one DCM now)
  • 16 channel 200MHz sampling rate with 16 to 32 demultiplexer
  • software controllable filter and demux operation
  • enabled input pull-up resistors on all 32 channels
  • synthesizes without warnings (sacrificed GBUF)

PC Client

  • support for 200MHz sampling rate
  • filter operation can be controlled by user
  • support for 16/32 channel wide data

0.3 (2006-05-05)

FPGA

  • operates at 100MHz
  • additional buffer for cleaner data hand-over between 200MHz filter and 100MHz base clock driven logic

PC Client

  • meta data (size, rate, trigger position) stored in files

0.2 (2006-05-01)

FPGA

  • operates at 80MHz
  • faster noise filter code (up to 180MHz)
  • SRAM write enable remains set across multiple writes
    (violates RAM specs, but appears to work pretty well)

PC Client

  • time line in diagram

0.1 (2006-04-29)

  • initial version (50MHz)
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